Job Description
ASIC and FPGA Design Engineer (AI Training) We’re offering a high-compensation, part-time remote contract opportunity for advanced hardware engineering experts to contribute to cutting-edge AI training projects. Pay is determined by the scope and technical complexity of the work, and the role is ideal for PhD students, PhD candidates, and other deeply technical specialists seeking flexible, meaningful project-based work in analog, RTL, ASIC/FPGA, computer architecture, and embedded systems. About the Role Looking for a Chip Design Engineer with ASIC or FPGA experience to help AI systems understand full chip design flows and system-level tradeoffs. What You Will Do • Design problems across the RTL-to-GDS flow • Evaluate AI-generated chip architectures and implementations • Build verification pipelines for synthesis, timing, and power analysis • Assess tradeoffs across power, performance, and area • Contribute to defining project scope in ambiguous, R&D-heavy environments Core Focus Areas • ASIC design flow from RTL to layout • FPGA system design and deployment • Floorplanning, synthesis, and timing closure • Low-power design techniques including clock gating and multi-Vt Required Qualifications • MS or PhD in Electrical or Computer Engineering • 3 plus years in ASIC or FPGA design • Experience with synthesis and timing tools • Strong Python skills for automation Relevant Tools • Yosys, OpenLane, OpenSTA, Vivado Preferred • Tape-out experience • Experience with DFT or physical design Pay: $75.00 - $150.00 per hour Work Location: Remote